Synchronous rectifier may be used in a large verity of electronic devices. These rectifiers may be used to convert a direct current (DC) from a first voltage to another voltage. Such rectifiers may also include various components, for example, transformers, to provide galvanic isolation. Careful timing of the rectifier may be used to reduce loss of energy in increase efficiency.
An example of a synchronous rectifier is one where transistors (e.g., MOSFETs) are used to create an H-bridge. This configuration may have four transistors forming a ‘full-bridge’ or two transistors forming a half-bridge.
The MOSFETs may be controlled by fixed delays and logic that create a time period when the current is forced to conduct through the body diode of the MOSFET. As the voltage across a diode is significantly larger than the MOSFET on resistance multiplied by the load current, a higher energy loss per switching cycle results in lower efficiency.
FIG. 1 illustrates a simplified block diagram of an electronic device having a secondary side ‘full-bridge’ synchronous rectifier topology where current flows through two series connected devices. In a particular application requiring the dc/dc converter to sustain a single failure of a semiconductor device without interrupting the output voltage bus, the output MOSFETs may be configured as a ‘full-bridge’ (see FIG. 1) where the transistors are activated in pairs (e.g., Q1-Q3 pair and Q2-Q4 pair). In this example, these pairs are activated using the DOT and NO_DOT signals.
FIG. 2 illustrates a simplified block diagram of an electronic device having a conventional low output voltage synchronous rectifier topology where current flow through one MOSFET. In this ‘half-bridge’ rectifier (see FIG. 2), only two MOSFETs (Q1 and Q2) are in parallel. Compared to a ‘half-bridge’ rectifier the energy loss of a ‘full-bridge’ rectifier is doubled because the current must flow through two devices in series (Q2 and Q4 when DOT is activated or Q1 and Q3 when NO_DOT is activated).
Common methods of timing synchronous rectifier for ‘full-bridge’ and ‘half-bridge’ output stages use complementary drive signals from the primary MOSFET drive signals. FIG. 5 illustrates a simplified block diagram of an electronic device having a conventional gate drive timing for a ‘full-bridge’ primary with a secondary synchronous rectifiers (no zero voltage switching on primary possible). In the ‘full-bridge’ configuration some time may be spent with all primary switches off (dead time) resulting in zero volts across the primary winding. The secondary side output inductor then forces current to flow through all secondary side switches. A preferred loss would be for all secondary switches to be ‘on’. Thus, a gate drive method is to provide complementary signals where one pair of primary side MOSFETs is labeled A and the other B and the secondary side gate drive is driven NOT_A and NOT_B such that the polarity of the windings is correct for power delivery as shown in FIG. 5.
FIG. 6 illustrates a simplified block diagram of an electronic device using an alternate method to achieve phase-shifted gate drive timing for a ‘full-bridge’ primary with secondary synchronous rectifiers (non-optimal). The two typical primary switching strategies are to 1) turn both primary switches off to create the pulse wave modulated (PWM) voltage across the primary or 2) to turn two switches on that force the winding to ‘zero volts’. For the second method of clamping the primary to zero voltage either both top or bottom switches can be turned on. Two standard methods to accomplish the clamping are the ‘phase shifted lull-bridge’ control method where the left and right bridge are driven by a 50% duty-cycle and a phase angle determined by the PWM voltage or an alternative which provides complementary drive signals to the left and right legs of the bridge as shown in FIG. 6. Both methods result in the same voltage and current waveforms imposed on the transformer but the latter is more robust and easier to implement.
When either NOT_A and NOT_B are changed from being high to either A or B being high, the current must change polarity in the windings. During this transition a period of time exists when the current remains in the polarity of the previous state before ‘crossing zero’ (see FIG. 3 which depicts a flowchart illustrating a conventional timing approach). Using the typical gate drive techniques, one secondary leg of the output MOSFETs would be turned off before the current crosses zero. A MOSFET has a ‘body diode’ which protects the switch from a large energy pulse (the current cannot instantly stop flowing without a large dissipation of energy) but results in the current moving from the low resistance MOSFET channel to the body diode.
This commutation time, or delay, results in several issues. One issue is that the delay causes a period of time when the current flows through the ‘body diode’ of the MOSFET reducing the power delivery efficiency. The body diode also exhibits charge storage resulting in additional energy loss, called ‘reverse recovery current’ or ‘recovery charge’. For low voltage outputs the percentage of additional power losses rises since the diode drop is a fixed voltage as compared to the variable output voltage. Thus, a typical 0.8 V diode drop is more significant to a 1 V output regulator than to a 5 V regulator output. The reverse recovery process by which charge needs to be removed from the body diode results in the MOSFET appearing to have a large capacitance which increases the turn off spike and results in potentially harmful stress to the MOSFET and additional power loss.
This problem is compounded with a ‘full-bridge’ output rectification as two diodes are present in series. What is needed is a synchronous rectifier configuration which is functional in low voltage outputs, improves the reliability of the circuit and prevents single faults from disturbing the power bus.